1. Field of the Invention
The present invention relates to a sequential pulse train generator and particularly to a sequential pulse train generator for liquid crystal displays (LCDs), which operates with a low-voltage clock signal supply.
2. Description of the Prior Art
In LCDs, a frame of image is formed by lines of pixels sequentially scanned by a gate driver. The gate driver must generate a sequential pulse train to drive the scan lines. Thus, a sequential pulse train generator is an essential element of an LCD.
FIG. 1 is a diagram showing a conventional sequential pulse train generator for the LCD. For the sake of clarity, only three stages are exemplified in FIG. 1 although the sequential pulse train generator may be composed of more stages. Each of the stages includes a shift register 111, 112 or 113, and a level shifter 121, 122 or 123. The shift register 111, 112 or 113 receives a clock signal CK and an inverted clock signal CKxe2x80x2. The shift register 111 in the first stage further receives an initial pulse train IN. The initial pulse train IN is sequentially delayed through the stages and its level is shifted by the level shifter 121, 122 and 123 so that a sequential pulse train having a sufficient pulse level is generated.
The resistances 131 and 132, and capacitances 151 and 152 of the transmission lines for the clock signal CK and CKxe2x80x2 cannot be zero. There are also resistances 141, 142 and 143, and capacitances 161, 162 and 163 on the output lines for the pulse train. These resistances and capacitances induce some power consumption in the LCD.
However, the power consumption of a transmission line is proportional to the amplitude of the signal there on. The conventional sequential pulse train generator needs a relatively high voltage clock supply, which induces high power consumption.
The object of the present invention is to provide a sequential pulse train generator operating with a low-voltage clock signal supply to reduce power consumption in transmission of the clock signal.
The present invention provides a sequential pulse train generator comprising a first and second dynamic shift register circuit, each of which has a first, second, third and fourth input terminal, and a first, second and third output terminal, first, second, third and fourth input terminal of the first dynamic shift register circuit coupled to receive an initial pulse train, the inverted initial pulse train, a clock signal and the inverted clock signal, the first output terminal of the first dynamic shift register circuit coupled to the first input terminal of the second dynamic shift register circuit, the third and fourth input terminal of the second dynamic shift register circuit coupled to receive the inverted clock signal and the clock signal, respectively, a first and second level shifter, each of which has a first and second input terminal, and an output terminal, the first and second input terminal of the first level shifter coupled to the second and third output terminal of the first dynamic shift register circuit, the output terminal of the first level shifter coupled to the first output terminal of the first dynamic shift register circuit, the first and second input terminal of the second level shifter coupled to the second and third output terminal of the second dynamic shift register circuit, the output terminal of the second level shifter coupled to the first output terminal of the second dynamic shift register circuit, respectively, and a first and second inverter having output terminals coupled to the output terminals of the first and second level shifter, and outputting a first and second sequential pulse train, the output terminal of the first inverter coupled to the second input terminal of the second dynamic shift register circuit.
The present invention further provides a sequential pulse train generator comprising a first, second and third dynamic shift register circuit, each of which has a first, second and third input terminal, and a first, second and third output terminal, the first, second and third input terminal of the first dynamic shift register coupled to receive an initial pulse train, the inverted initial pulse train and a clock signal, the first output terminal of the first dynamic shift register circuit coupled to the second input terminal of the third dynamic shift register circuit, the third input terminal of the second dynamic shift register coupled to receive the inverted clock signal, the third input terminal of the third dynamic shift register circuit coupled to receive the clock signal, a first, second and third level shifter, each of which has a first and second input terminal, and an output terminal, the first and second input terminal of the first level shifter coupled to the second and third output terminal of the first dynamic shift register circuit, the first and second input terminal of the second level shifter coupled to the second and third output terminal of the second dynamic shift register circuit, the first and second input terminal of the third level shifter coupled to the second and third output terminal of the third dynamic shift register circuit, and a second, third, fourth, fifth, sixth and seventh inverter, input terminals of the second, third and fourth inverter coupled to the output terminals of the first, second and third level shifter, output terminals of the second and third inverter coupled to the first input terminals of the second and third dynamic shift register circuit, input terminals of the fifth, sixth and seventh inverter coupled to the output terminals of the second, third and fourth inverter, an output terminal of the fifth inverter coupled to the second input terminal of the second dynamic shift register circuit, the output terminals of the fifth, sixth and seventh inverter outputting a first, second and third sequential pulse train, respectively.